`ifndef UDLY
`define UDLY 1
`endif
module chdl_assert(

);
//parameter declare
//port declare
//channel declare
//wire declare
//port wire declare
//register declare
//register init and update
logic assert_fail_flag;
initial begin
  assert_fail_flag = 1'h0;
end

logic [2047:0] assert_message;
initial begin
  assert_message = 2048'h0;
end

//cell instance
endmodule
